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Product Specification
PE43501
Product Description
The PE43501 is a HaRPTM-enhanced, high linearity, 5-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 7.75 dB attenuation range in 0.25 dB steps. The Peregrine 50 RF DSA provides a serial-addressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with Vdd due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. The PE43501 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 50 RF Digital Attenuator 5-bit, 7.75 dB, DC-6.0 GHz Features * HaRPTM-enhanced UltraCMOSTM device
* Attenuation: 0.25 dB steps to 7.75 dB * High Linearity: Typical +58 dBm IP3
Excellent low-frequency performance * 3.3 V or 5.0 V Power Supply Voltage
* Fast switch settling time * Programming Modes:
* * *
*
Direct Parallel Latched Parallel Serial-Addressable: Program up to eight addresses 000 - 111
* High-attenuation state @ power-up (PUP) * CMOS Compatible
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
* No DC blocking capacitors required * Packaged in a 32-lead 5x5x0.85 mm QFN
Figure 2. Functional Schematic Diagram
Switched Attenuator Array RF Input RF Output
Parallel Control Serial In
5
Control Logic Interface CLK LE
A0
A1
A2
P/S
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PE43501
Product Specification
Table 1. Electrical Specifications @ +25C, VDD = 3.3 V or 5.0 V
Parameter
Frequency Range Attenuation Range Insertion Loss 0 dB - 7.75 dB Attenuation settings 0dB to 3.5 dB Attenuation Settings 3.75 dB to 7.75 dB Attenuation Settings 0dB to 7.75dB Attenuation Settings 0.25 dB Step DC 6 GHz DC < 4 GHz 4 GHz 6 GHz 4 GHz 6 GHz 4 GHz 6 GHz DC - 6 GHz All States Input Two tones at +18 dBm, 20 MHz spacing DC - 6 GHz 20 MHz - 6 GHz 20 MHz - 6 GHz 1 MHz 50% CTRL to 10% / 90% RF 10% / 90% RF RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. 30 18 9 32 58 -110 10 650 400 4
Test Conditions
Frequency
Min
Typical
DC - 6 0 - 7.75 2.3
Max
Units
GHz dB
2.8 (0.15+4%) +0.2+4% +0.3+4% -0.2 - 4%
dB dB dB dB dB dB deg dBm dBm dBm mVpp ns ns s
Attenuation Error
Return Loss Relative Phase P1dB IIP3 Typical Spurious Value Video Feed Through Switching Time RF Trise/Tfall Settling Time
Performance Plots Figure 3. 0.25 dB Step Error vs. Frequency*
200 MHz 2200 MHz 0.7 900 MHz 3000 MHz 1800 MHz 5400 MHz
Figure 4. 0.25dB Attenuation vs. Attenuation State Attenuation
8 7
900 MHz 1800 MHz 2200 MHz 3000 MHz 5400 MHz 5800 MHz
0.6 0.5 Step Error (dB.)
Attenuation dB
6 5 4 3 2 1 0 0 1
0.4 0.3
0.2
0.1
0.0 0 1 2 3 4 5 6 7 8 Attenuation Setting (dB.)
2
3
4
5
6
7
8
Attenuation State
*Monotonicity is held so long as step-error does not cross zero.
Figure 5. 0.25 dB Major State Bit Error
0.25dB State 2.0 1.5 1.0 Bit Error (dB.) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0.0 1.0 2.0 3.0 4.0 Frequency (GHz) 5.0 6.0 7.0 8.0 2dB State 0.5 dB State 4dB State 1dB State 7.75dB State
Figure 6. 0.25 dB Attenuation Error vs. Frequency
200 MHz 3000 MHz 1.00 0.75 0.50 Attenuation Error (dB.) 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0 1 2 3 4 5 6 7 8 Attenuation Setting (dB.) 900 MHz 4000 MHz 1800 MHz 6000 MHz 2200 MHZ
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Figure 7. Insertion Loss vs. Temperature
-40C 0 -0.5 -1 Insertion Loss (dBm.) +25C +85C
Figure 8. Input Return Loss vs. Attenuation: T = +25C
0 -5 -10 Return Loss (dB.) -15 -20 -25 -30 -35 -40 -45 -50 0dB 2dB 0.25dB 4dB 0.5dB 7.75dB 1dB
-1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 0.0 1.0 2.0 3.0 4.0 5.0 Frequency (GHz) 6.0 7.0 8.0 9.0
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Figure 9. Output Return Loss vs. Attenuation: T = +25C
0dB 2dB
0
Figure 10. Input Return Loss vs. Temperature: 7.75 dB State
-40C 0 -10 Return Loss (dB.) -20 -30 -40 -50 -60 25C 85C
0.25dB 4dB
0.5dB 7.75dB
1dB
-10
Return Loss (dB.)
-20
-30
-40
-50
-60 0 1 2 3 4 5 6 7 8 9 Frequency (GHz.)
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Figure 11. Output Return Loss vs. Temperature: 7.75 dB State
-40C 0 -10 -20 Return Loss (dB.) -30 -40 -50 -60 -70 0 1 2 3 4 5 6 7 8 9 Frequency (GHz.) 25C 85C
Figure 12. Relative Phase vs. Frequency
0dB
16 14 12 10 8 6 4 2 0 0 1
0.25dB
0.5dB
1dB
2dB
4dB
7.75dB
Relative Phase Error (Deg.)
2
3
4 Frequency (GHz.)
5
6
7
8
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PE43501
Product Specification
Figure 13. Relative Phase vs. Temperature: 7.75 dB State
900 MHz 4.5 4.0 3.5 3.0 Phase (deg.) 2.5 2.0 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 Temperature (Deg. C.) 1800 MHz 3000 MHz
Figure 14. Attenuation Error vs. Attenuation Setting: 900 MHz
900 MHz @ T=+25 C
0.50
900 MHz @ T= -40C
900 MHz @ T= +85C
0.30 Attenuation Error (dB.)
0.10
-0.10
-0.30
-0.50 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Attenuation Setting (dB.)
Figure 15. Attenuation Error vs. Attenuation Setting: 1800 MHz
1800 MHz @ T= +25C 0.50 1800 MHz @ T= -40C 1800 MHz @ T= +85C
Figure 16. Attenuation Error vs. Attenuation Setting: 3000 MHz
3000 MHz @ T= +25C 0.50 3000 MHz @ T= -40C 3000 MHz @ T= +85C
0.30 Attenuation Error (dB.)
Attenuation Error (dB.)
0.30
0.10
0.10
-0.10
-0.10
-0.30
-0.30
-0.50 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
-0.50 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Attenuation Setting (dB.)
Attenuation Setting (dB.)
Figure 17. Input IP3 vs. Frequency
0dB 70 65 60 Input IP3 (dBm.) 55 50 45 40 35 30 0 1000 2000 3000 4000 5000 6000 7000 Frequency (MHz.) 0.25dB 0.5dB 1dB 2dB 4dB
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Figure 18. Pin Configuration (Top View)
C0.25 GND GND C0.5
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.
C1
C2
C4
32
31
30
29
28
27
26
NC VDD P/S A0 GND GND RF1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SI
25 24 23 22
CLK LE A1 A2 GND GND RF2 GND
Exposed Solder pad
21 20 19 18 17
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43501 in the 32-lead 5x5 QFN package is MSL1.
GND
GND
GND
GND
GND
GND
GND
GND
Switching Frequency
The PE43501 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states.
Description
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5, 6, 8-17, 19, 20, 26, 27 7 18 21 22 23 24 25 28 29 30 31 32 Paddle
Pin Name
N/C VDD P/S A0 GND RF1 RF2 A2 A1 LE CLK SI C4 C2 C1 C0.5 C0.25 GND
No Connect Power supply pin Serial/Parallel mode select A0 connection Ground RF1 port RF2 port A2 connection A1 connection Latch Enable input Serial interface clock input Serial Interface input Attenuation control bit, 4 dB Attenuation control bit, 2 dB Attenuation control bit, 1 dB Attenuation control bit, 0.5 dB Attenuation control bit, 0.25 dB Ground for proper operation
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package must be grounded for proper device operation.
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PE43501
Product Specification
Table 3. Operating Ranges
Parameter VDD Power Supply Voltage VDD Power Supply Voltage IDD Power Supply Current Digital Input High PIN Input power (50): 1 Hz 20 MHz 20 MHz 4 GHz TOP Operating temperature range Digital Input Low Digital Input Leakage1 Note 1. Input leakage current per Control pin -40 0 25 2.6 Min 3.0 Typ 3.3 5.0 70 5.5 350 5.5 See fig. 19 +23 85 1 15 Max Units V V A
Table 4. Absolute Maximum Ratings
Symbol VDD VI PIN V TST dBm dBm VESD C Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) V A Parameter/Conditions Power supply voltage Voltage on any Digital input Input power (50) 1 Hz 20 MHz 20 MHz 4 GHz Storage temperature range ESD voltage (HBM)1 ESD voltage (Machine Model) -65 Min -0.3 -0.3 Max 6.0 5.8 See fig. 19 +23 150 500 100 Units V V dBm dBm C V V
Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
Figure 19. Maximum Power Handling Capability: Z0 = 50
30.0
25.0
20.0 Pin dBm
15.0
10.0
5.0
0.0 1.0E+03
1.0E+04
1.0E+05
1.0E+06 Hz
1.0E+07
1.0E+08
1.0E+09
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Table 5. Control Voltage
State
Low High
Table 8. Address Word Truth Table
Bias Condition
Address Word A7 (MSB)
X X X X
0 to +1.0 Vdc at 2 A (typ) +2.6 to +5 Vdc at 10 A (typ)
A6
X X X X X X X X
A5
X X X X X X X X
A4
X X X X X X X X
A3
X X X X X X X X
A2
L L L L H H H H
A1
L L H H L L H H
A0
L H L H L H L H
Address Setting
000 001 010 011 100 101 110 111
Table 6. Latch and Clock Specifications
Latch Enable
X
X X X X
Shift Clock
X
Function
Shift Register Clocked Contents of shift register transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting D4
L L L L L H H
Table 9. Serial Attenuation Word Truth Table
Attenuation Setting RF1-RF2
Reference I.L. 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 7.75 dB
Attenuation Word D7
X X X X X X X
D3
L L L L H L H
D2
L L L H L L H
D1
L L H L L L H
D0
L H L L L L H
D6
L L L L L L L
D5
L L L L L L L
D4
L L L L L H H
D3
L L L L H L H
D2
L L L H L L H
D1
L L H L L L H
D0 (LSB)
L H L L L L H
Attenuation Setting RF1-RF2
Reference I.L. 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 7.75 dB
Table 10. Serial-Addressable Register Map
MSB (last in) Q15 A7 Q14 A6 Q13 A5 Q12 A4 Q11 A3 Q10 A2 Bits can either be set to logic high or logic low Q9 A1 Q8 A0 Q7 D7 Q6 D6 Q5 D5 Q4 D4 Q3 D3 Q2 D2 LSB (first in) Q1 D1 Q0 D0
Address Word
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 3.75 dB state at address 3: Address Word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary 4 * 3.75 dB 15 0001111 Serial Input: XXXXX011X0001111
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PE43501
Product Specification
Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43501. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 21 (Parallel Interface Timing Diagram), Table 12 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 21) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial interface is a 16-bit serial-in, parallelout shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 20 illustrates a example timing diagram for programming a state. It is recommended that all parallel control inputs be grounded when the DSA is used in serial mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the attenuation word. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the Serial-Addressable register is illustrated in Table 10. The serial-addressable timing diagram is illustrated in Fig. 20. Power-up Control Settings The PE43501 will always initialize to the maximum attenuation setting (7.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 7.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-s delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (7.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state).
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Figure 20. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
TDISU TDIH
ADD[2:0] P/S
VALID TASU TAH
TPSSU
TPSH
SI
TSISU TSIH
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
A[0]
A[1]
A[2]
CLK
TCLKL TCLKH TLESU
LE
TLEPW TPD VALID
DO[6:0]
Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU TPSH VALID TDISU TDIH
DI[6:0]
LE
TLEPW
DO[6:0]
TDIPD
VALID TPD
Table 11. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
FCLK TCLKH TCLKL TLESU TLEPW TSISU TSIH TDISU TDIH TASU TAH TPSSU TPSH TPD
Table 12. Parallel and Direct Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
TLEPW TDISU TDIH
Parameter
Serial clock frequency Serial clock HIGH time Serial clock LOW time Last serial clock rising edge setup time to Latch Enable rising edge Latch Enable min. pulse width Serial data setup time Serial data hold time Parallel data setup time Parallel data hold time Address setup time Address hold time Parallel/Serial setup time Parallel/Serial hold time Digital register delay (internal)
Min
30 30 10 30 10 10 100 100 100 100 100 100 -
Max
10 10
Unit
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Latch Enable minimum pulse width Parallel data setup time Parallel data hold time Parallel/Serial setup time Parallel/Serial hold time Digital register delay (internal) Digital register delay (internal, direct mode only)
Min
30 100 100 100 100 -
Max
10 5
Unit
ns ns ns ns ns ns ns
TPSSU TPSIH TPD TDIPD
Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at10 MHz to verify fclk specification. Document No. 70-0251-03 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13
PE43501
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE43501 Digital Step Attenuator. Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J1 & Serial header pin and set the D0-D4 SP3T switches to the `MIDDLE' toggle position. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J1 and Serial header pins. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to logic high. Switches D0-D4 are SP3T switches which enable the user to manually program the parallel bits. When any input D0-D4 is toggled `UP', logic high is presented to the parallel input. When toggled `DOWN', logic low is presented to the parallel input. Setting D0-D4 to the `MIDDLE' toggle position presents an OPEN, which forces an on-chip logic low. Table 7 depicts the parallel programming truth table and Fig. 21 illustrates the parallel programming timing diagram. Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that LatchedParallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now
Figure 22. Evaluation Board Layout
Peregrine Specification 101-0312
Note: Reference Fig. 23 for Evaluation Board Schematic
the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from 0V to VDD and back to 0V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. Serial-Addressable Programming Procedure Position the Parallel/Serial (P/S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A0-A2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then 000 become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled.
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Figure 23. Evaluation Board Schematic
Peregrine Specification 102-0381
VDD
4
6
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2 D6 3
_
P/S
D0
D1
D2
D3
D4
D5
D6
5
3
3
3
3
3
D3
D4
P/S
D0
D1
J1 HEADER 14
_
2 4 6 8 10 12 14
2 4 6 8 10 12 14
1 3 5 7 9 11 13
1 3 5 7 9 11 13
D0 D1 D2 D3 D4 D5 D6
SERIAL HEADER 4
D2
D5
3
4
SI LE
CLK 1 2 3 4
CLOCK SI LE GND VDD
C5 100pF C6 100pF VDD J3 CON2 1 2 C4 100pF
C3 100pF C2 100pF
C1 100pF A0_2 A1_2 A2_2
ADD A0 VDD A1 VDD A2 VDD HEADER3X3 24 23 22 21 20 19 18
J5 Z=50 Ohm SMA
D1
D2
D3
D4
D5
C0 100pF 1 VDD
32
31
30
29
28
27
26
D6
A2_1 A1_1 A0_1
D0
CP25
C16
CP5
C1
C2
C4
C8
SI
CLK LE A1
25
GND
J2 VSS A1 A2 R1 0 OHM R2 0 OHM C11 0.1uF C12 100pf 1 2 CON2
_
2 3 4 5
VDD PS A0 GND GND RF1 U1
PE43XOX DSA 50 OHM 5X5 MLPQ32
C9 0.1F
C10 100pF
P/S
C8 100pF
C13 100pF
C14 100pF
A0
A2 VSS GND RF2
J4 SMA
Z=50 Ohm
6 7 8
1
1
2
GND
GND
GND
GND
GND
GND
SMA
SMA
1
1
GND
10
11
12
13
14
15
2
2
Note: Capacitors C1-C8, C13, & C14 may be omitted. Pin 26 & 27 are ground.
Figure 24. Package Drawing
QFN 5x5 mm
MAX 0.900 0.850 0.800
A
NOM MIN
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16
9
GND
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2
J6
De-embeding trace Z=50 Ohm
J7
GND
GND 17
PE43501
Product Specification
Figure 24. Tape and Reel Drawing
Tape Feed Direction
Pin 1
Top of Device
Device Orientation in Tape
Figure 25. Marking Specifications
43501 YYWW ZZZZZ
Table 13. Ordering Information Order Code Part Marking
PE43501MLI PE43501MLI-Z EK43501-01 43501 43501 43501
YYWW = Date Code ZZZZZ = Last five digits of Lot Number
Description
PE43501 G - 32QFN 5x5mm-75A PE43501 G - 32QFN 5x5mm-3000C PE43501 - 32QFN 5x5mm-EK
Package
Green 32-lead 5x5mm QFN Green 32-lead 5x5mm QFN Evaluation Kit
Shipping Method
Bulk or tape cut from reel 3000 units / T&R 1 / Box
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Document No. 70-0251-03
UltraCMOSTM RFIC Solutions
PE43501
Product Specification
Sales Offices
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Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
(c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 13
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
Document No. 70-0251-03 www.psemi.com

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